The Verification IP for PHY is part of the Cadence Verification Suite and supports the company’s Intelligent System Design strategy, enabling SoC design excellence through best-in-class IP. The new Cadence VIP for PHY offers a comprehensive verification solution for the most complicated and challenging physical-layer interfaces and protocols, including PIPE 5.2 for PCI Express (PCIe) 5.0, USB3 and USB4, DFI for LPDDR4, DDR5 and HBM2E, and MIPI D-PHY/C-PHY for CSI-2 2.0 and DSI 2.0.
With the PHY VIP, companies can shorten time to market through advanced built-in capabilities for PHY verification such as PHY-level timing checks, the ability to drive protocol-aware and protocol-agnostic traffic for exhaustive testing, and use a built-in scoreboard for analyzing receive path, transmit path and loopback. The solution also enables control over jitter, spread spectrum clock and bit error rate verification.
Additionally, the solution includes Cadence TripleCheck technology, which provides users with a PHY-related verification plan that is linked to the specification as well as comprehensive coverage models and a test suite to ensure compliance with the interface specification.
“Our PHY team has successfully utilized Cadence VIP for verification of various protocols such as USB3 and PCIe 4.0, enabling us to quickly deliver unique and innovative designs for a broad range of applications,” says Realtek’s Vice President and Spokesman, Yee-Wei Huang. “With the complexity inherent in verifying PHY designs, Cadence VIP for PHY addresses a critical and challenging verification task and provides the speed and accuracy we need to help our customer’s time to market.”
“PHY verification requires unique methods to ensure that all timing, power and throughput requirements are met in various conditions,” states Moshik Rubin, Verification IP product management group director, System and Verification Group at Cadence. “With the industry’s first dedicated VIP for PHY, we’re enabling our customers to verify their PHY designs effectively, ensuring the designs comply with the standard specification and meet application-specific performance metrics to provider the fastest path to IP verification closure.”