Cadence Announces Industry’s First Verification IP for PHY Covering Multiple Protocols

Cadence Design Systems announced the availability of the industry’s first Verification IP (VIP) that enables comprehensive and fast verification of the physical layer (PHY) for complex protocols such as PCIe 5.0, USB3/4, DDR5, LPDDR5, HBM and MIPI CSI-2 and DSI 2.0. This allows companies to thoroughly test and optimize their PHY designs, accelerating development.