Renesas is among the first in the industry to independently develop a CPU core for the 32-bit general-purpose RISC-V market, providing an open and flexible platform for new consumer electronics applications, and particularly voice-driven human-machine interface systems.
RISC-V is an open ISA which is quickly gaining popularity in the semiconductor industry, due to its flexibility, scalability, power efficiency and open ecosystem. While many MCU providers have recently created joint investment alliances to accelerate their development of RISC-V products, Renesas has already developed a new RISC-V core on its own. This versatile CPU can serve as a main application controller, a complementary secondary core in SoCs, in on-chip subsystems, or even in deeply embedded ASSPs.
This positions Renesas as a leader in the emerging RISC-V market, following previous introductions of its 32-bit voice-control and motor-control ASSP devices, as well as the RZ/Five 64-bit general purpose microprocessors (MPUs), which were built on CPU cores developed by Andes Technology Corp.
"Renesas takes pride in offering embedded processing solutions for the broadest range of customers and applications," says Daryl Khoo, Vice President of the IoT Platform Division at Renesas. "This new core extends our leadership in the RISC-V market and uniquely positions us to deliver more solutions that accommodate a diverse range of requirements."
"We congratulate Renesas on achieving its recent milestone in 32-bit RISC-V MCU architecture development," says Calista Redmond, CEO at RISC-V International. "This achievement exemplifies how RISC-V ecosystem partners, such as Renesas, are rapidly advancing RISC-V innovation. Our RISC-V community now spans 70 countries with more than 4,000 members, and we eagerly anticipate further innovations emerging from this dynamic, expanding market."
The Renesas RISC-V CPU achieves an impressive 3.27 CoreMark/MHz performance, outperforming similar architectures on the market. It includes extensions to improve performance, while reducing code size and the required toolchains are available as part of the necessary infrastructure to develop and deploy a solution. Developers will be able to benefit from either the Renesas e2 studio environment with its configuration plugins or any major commercial third-party IDE supporting RISC-V based MCUs. These are all ready to use.
As Giancarlo Parodi, Principal Product Marketing Engineer at Renesas explains, the CPU implementation is not just simulated, its features have been designed and validated in a real silicon product implementation. Initial benchmarks showed an impressive 3.27 CoreMark/MHz performance while using an open source LLVM-based compiler toolchain, outperforming comparable architectures available on the market.
Renesas is sampling devices based on the new core to select customers, with plans to launch its first RISC-V-based MCU and associated development tools in Q1 2024. Details of the new MCU will be published at that time.
www.renesas.com/risc-v
www.renesas.com
