Renesas Unveils Its Own First Generation 32-bit RISC-V CPU Core

Renesas Electronics announced that it has designed and tested a 32-bit CPU core based on the open-standard RISC-V instruction set architecture (ISA). The new RISC-V Core extends Renesas' industry-leading embedded processing portfolio and expands the company's position as a leading supplier of advanced semiconductor solutions. The new RISC-V CPU core will complement Renesas' existing IP portfolio of 32-bit microcontrollers (MCUs), including the proprietary RX Family and the RA Family based on the Arm Cortex-M architecture.

Renesas extended its RISC-V embedded processing portfolio with the first RISC-V MCU designed for voice-controlled HMI (human-machine interface) systems. The new R9A06G150 32-bit ASSP (Application Specific Signal Processor), developed in collaboration with RISC-V ecosystem partners, provides a complete, cost-effective, production-ready voice-control system solution that eliminates the need for RISC-V tools and upfront software investment.

Flex Logix Technologies and CEVA, have announced the world’s first successful silicon implementation using Flex Logix’s EFLX embedded FPGA (eFPGA) connected to a CEVA-X2 DSP instruction extension interface. Enabling flexible and changeable instruction sets to meet demanding and changing processing workloads, the ASIC, known as SOC2, was designed and taped out in a TSMC 16nm technology by Bar-Ilan University SoC Lab, as part of the HiPer Consortium, backed by the Israeli Innovation Authority (IIA).

RISC-V is bringing together different companies and industries, combining a modular technical approach with an open license business model for the RISC-V Instruction Set Architecture (ISA). RISC-V International, the global non-profit open hardware standards organization, incorporated in Switzerland, just announced a new set of specifications that will be key for advanced audio applications using machine learning (ML).