Renesas Unveils Its Own First Generation 32-bit RISC-V CPU Core

Renesas Electronics announced that it has designed and tested a 32-bit CPU core based on the open-standard RISC-V instruction set architecture (ISA). The new RISC-V Core extends Renesas' industry-leading embedded processing portfolio and expands the company's position as a leading supplier of advanced semiconductor solutions. The new RISC-V CPU core will complement Renesas' existing IP portfolio of 32-bit microcontrollers (MCUs), including the proprietary RX Family and the RA Family based on the Arm Cortex-M architecture.

Qualcomm and Google are extending their collaboration on wearables by developing a RISC-V Snapdragon Wear platform that will power next-generation Wear OS solutions. According to the announcement, this is an important first milestone to bring RISC-V compatible CPUs to the Android ecosystem, while Google pursues is strategy of continuously copy everything that Apple does, and help others do the same.

Dave Erickson built his first multi-zone audio system in the early 1990s using C microprocessor code he developed on Freescale MC68HC11 microprocessors. In early 2014, he detailed how he upgraded the eight-zone system, which uses microprocessor-controlled analog circuitry.