Cadence Announces New Tensilica FloatingPoint DSP Family for Low Power AI/ML

Cadence Design Systems unveiled the Cadence Tensilica FloatingPoint DSP family, optimized for power, performance and area (PPA). The new DSP IP cores extend from small, ultra-low power to very high performance and are well-suited for a broad array of applications, from energy-efficient solutions for battery powered devices to artificial intelligence/machine learning (AI/ML), sensor fusion, object tracking and augmented reality applications in the mobile, automotive, and consumer markets.
The new family is comprised of four cores: the Tensilica FloatingPoint KP1 DSP, the Tensilica FloatingPoint KP6 DSP, the Tensilica FloatingPoint KQ7 DSP and the Tensilica FloatingPoint KQ8 DSP. Cadence received early feedback from developers, with evaluations demonstrating significant benefits in power, performance and area. The new family offers up to 40% area savings for mobile, automotive, consumer and hyperscale computing markets.

Tensilica FloatingPoint DSPs share a common instruction set architecture (ISA) with existing Tensilica DSPs’ optional vector floating-point unit (VFPU), promoting software portability and reusability while enabling easy offloading of floating-point workloads. Scalable from 128-bit SIMD to 1024-bit SIMD on both the Tensilica Xtensa LX and NX platforms, the new FloatingPoint DSPs deliver a 25% improvement in fused multiply-add (FMA) operations compared to Tensilica fixed-point DSPs with the VFPU add-on, contributing to greater operational throughput. 

Performance can be further enhanced and differentiated using the Tensilica Instruction Extension (TIE) language. In addition, the FloatingPoint DSPs offer up to 40% area savings compared to the similar class of fixed-point DSPs with VFPUs.
 
High-performance software tools accompanying the new DSPs provide effective auto-vectorization that helps optimize the scalar code to utilize the vector floating-point units with minimal to no manual effort. Support for optimized Eigen, NatureDSP, simultaneous location and mapping (SLAM) and math software libraries enables easier development of high-performance software. The Tensilica FloatingPoint DSPs offer a software development environment that enables seamless migration of the existing floating-point common software stack to the new Tensilica FloatingPoint DSPs and between the FloatingPoint DSPs within the family.

“Floating-point numbers are used widely in modern computations across a broad range of compute-intensive applications, and the need for floating-point processing is growing,” says Larry Przywara, senior group director, Tensilica marketing at Cadence. “Energy-efficient, cost-effective and high-performance DSPs designed specifically for floating-point-centric computation are critical for developing competitive and differentiated products. The scalable Tensilica FloatingPoint DSP family provides optimal PPA for these floating-point computations, regardless of the application. These DSPs are an example of how Cadence is applying our computational software prowess to hardware to solve our customers’ design challenges.”

The Tensilica FloatingPoint KP1 DSP, Tensilica FloatingPoint KP6 DSP, Tensilica FloatingPoint KQ7 DSP and Tensilica FloatingPoint KQ8 DSP are all in general availability now.
www.cadence.com/go/tensilicafloatingpoint