Western Digital Announces Plans to Open Source New RISC-V SweRV Core to Accelerate RISC-V Processor Development

During the RISC-V Summit, in Santa Clara, CA, Western Digital announced three new open-source innovations designed to support Western Digital’s internal RISC-V development efforts and those of the growing RISC-V ecosystem. In his keynote address, Western Digital’s Chief Technology Officer Martin Fink unveiled plans to release a new open source RISC-V core, an open standard initiative for cache coherent memory over a network and an open source RISC-V instruction set simulator.

Microchip Technology, via its Microsemi Corporation subsidiary, extended its Mi-V ecosystem by unveiling the architecture for a new class of SoC FPGAs that combine the industry's lowest power mid-range PolarFire FPGA family with a complete microprocessor subsystem based on the open, royalty-free RISC-V instruction set architecture (ISA). Demonstrations took place during RISC-V Summit (Dec. 4-5) to show size, power and performance benefits of integrating PolarFire SoC's Hard CPU Subsystem with Programmable Logic.

Audio and voice signal processing specialists CEVA announced that the complete RivieraWaves suite of Bluetooth 5 (low energy and dual mode) and Wi-Fi 802.11a/b/g/n/ac/ax intellectual property (IP) platforms are now offered with an optional integrated open-source RISC-V MCU. These integration-ready system solutions are ideal for those manufacturers seeking freedom from standard 3rd party processor architectures.