All items tagged with RISC-V (12)

November 22, 2024 by Joao Martins

Ubitium Debuts Workload-Agnostic, Universal RISC-V Microprocessor

Ubitium developed a breakthrough universal processor that consolidates all processing into a single, affordable chip that is able to adapt to any type of workload — from simple control logic to massive parallel data flow processing. Leveraging a RISC-V architecture, the processor could eliminate the need for multiple specialized chips, enabling advanced AI on device, at no additional cost. This would be ideal for adaptive audio, speech recognition and AI-enabled DSP in consumer electronics.

Microchip Technology Launches RISC-V Multi-Core 64-Bit Microprocessors

July 10, 2024 by Cristina Costa

Microchip Technology Launches RISC-V Multi-Core 64-Bit Microprocessors

Real-time, compute intensive applications such as fully adaptive noise cancellation, voice separation and Machine Learning (ML) are pushing the boundaries of embedded processing requirements, demanding more power-efficiency, hardware-level security and high reliability at the edge. With the launch of its PIC64 portfolio, Microchip Technology expanded its computing range to meet this rising demands.

Renesas Unveils Its Own First Generation 32-bit RISC-V CPU Core

December 4, 2023 by Joao Martins

Renesas Unveils Its Own First Generation 32-bit RISC-V CPU Core

Renesas Electronics announced that it has designed and tested a 32-bit CPU core based on the open-standard RISC-V instruction set architecture (ISA). The new RISC-V Core extends Renesas' industry-leading embedded processing portfolio and expands the company's position as a leading supplier of advanced semiconductor solutions. The new RISC-V CPU core will complement Renesas' existing IP portfolio of 32-bit microcontrollers (MCUs), including the proprietary RX Family and the RA Family based on the Arm Cortex-M architecture.

Qualcomm to Bring RISC-V Based Wearable Platform to Google's Wear OS

October 17, 2023 by Joao Martins

Qualcomm to Bring RISC-V Based Wearable Platform to Google's Wear OS

Qualcomm and Google are extending their collaboration on wearables by developing a RISC-V Snapdragon Wear platform that will power next-generation Wear OS solutions. According to the announcement, this is an important first milestone to bring RISC-V compatible CPUs to the Android ecosystem, while Google pursues is strategy of continuously copy everything that Apple does, and help others do the same.

New Renesas RISC-V Voice-Control ASSP Allows Differentiated Applications with Voice Recognition

March 31, 2023 by Cristina Costa

New Renesas RISC-V Voice-Control ASSP Allows Differentiated Applications with Voice Recognition

Renesas extended its RISC-V embedded processing portfolio with the first RISC-V MCU designed for voice-controlled HMI (human-machine interface) systems. The new R9A06G150 32-bit ASSP (Application Specific Signal Processor), developed in collaboration with RISC-V ecosystem partners, provides a complete, cost-effective, production-ready voice-control system solution that eliminates the need for RISC-V tools and upfront software investment.

CEVA Audio DSPs and Audio Front-End Software Available Through Intel Pathfinder for RISC-V Program

December 12, 2022 by audioXpress Staff

CEVA Audio DSPs and Audio Front-End Software Available Through Intel Pathfinder for RISC-V Program

CEVA announced that it will make its CEVA-BX1 and CEVA-BX2 Audio DSPs and audio front-end software stack available for commercial developers through the Intel Pathfinder for RISC-V ecosystem. A Strategic Member of RISC-V International, CEVA is making its audio DSPs and software stack accessible for prototyping and production design through the Intel FPGA based pre-silicon development platform.

December 7, 2021 by audioXpress Staff

RISC-V International Ratifies 15 New Specifications Opening Up New Possibilities for RISC-V Designs

RISC-V is bringing together different companies and industries, combining a modular technical approach with an open license business model for the RISC-V Instruction Set Architecture (ISA). RISC-V International, the global non-profit open hardware standards organization, incorporated in Switzerland, just announced a new set of specifications that will be key for advanced audio applications using machine learning (ML).

Renesas and SiFive Partner to Jointly-Develop Next-Generation High-End RISC-V Solutions for Automotive Applications

April 22, 2021 by audioXpress Staff

Renesas and SiFive Partner to Jointly-Develop Next-Generation High-End RISC-V Solutions for Automotive Applications

Renesas Electronics, a leading supplier of advanced semiconductor solutions, and SiFive, specialized in RISC-V processors and silicon solutions, announced a strategic partnership to jointly develop next-generation, high-end RISC-V solutions for automotive applications. The partnership will also include SiFive licensing the use of their RISC-V core IP portfolio to Renesas.

Microchip Launches Industry’s First SoC FPGA Development Kit Based on the RISC-V Instruction Set Architecture

September 18, 2020 by audioXpress Staff

Microchip Launches Industry’s First SoC FPGA Development Kit Based on the RISC-V Instruction Set Architecture

The rising adoption of the free and open RISC-V Instruction Set Architecture (ISA) is driving the need for an affordable, standardized development platform that embeds RISC-V technology and leverages the diverse RISC-V ecosystem. To meet this need, Microchip Technology is offering the industry’s first RISC-V based System-on-Chip (SoC) Field-Programmable Gate Array (FPGA) development kit for its own low-power, low-cost, PolarFire SoC FPGA.

Western Digital Announces Plans to Open Source New RISC-V SweRV Core to Accelerate RISC-V Processor Development

December 5, 2018 by Cristina Costa

Western Digital Announces Plans to Open Source New RISC-V SweRV Core to Accelerate RISC-V Processor Development

During the RISC-V Summit, in Santa Clara, CA, Western Digital announced three new open-source innovations designed to support Western Digital’s internal RISC-V development efforts and those of the growing RISC-V ecosystem. In his keynote address, Western Digital’s Chief Technology Officer Martin Fink unveiled plans to release a new open source RISC-V core, an open standard initiative for cache coherent memory over a network and an open source RISC-V instruction set simulator.

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